This invention relates generally to semiconductor integrated circuits and more particularly to self-timed digital logic circuits.
As is known in the art, modern computer systems and other types of digital systems employ logic circuits including microprocessor and memories to implement various functions in a digital manner. One type of logic circuit uses control logic which is self-timed. That is, the logic circuit uses no external reference synchronization signal commonly referred to as a clock signal but rather detects an occurrence of an event to start a control sequence to assert and de-assert as necessary control signals to control a particular logic circuit. An example of a logic circuit which employs self-timed control logic is the static random access memory.
As it is known, a static random access memory is employed in computer systems particularly in cache memories of computer systems to provide quick yet random access to stored data. A typical standard static random access memory (SRAM) comprises address and data interface circuits and control logic which provides self-timed signals to address and enable a memory array which is typically comprised of a very large plurality of static storage cells. In a SRAM during either a read or write to the memory an address is fed to an address decoder in the SRAM to provide row and column address signals to address the memory array. The address is also fed to a pulse generator circuit to generate a pulse of controlled pulse width in response to a change in one of the address signals. This pulse of controlled pulse width is used to initiate a control and timing sequence which provides enable signals to the array to enable data to be stored in the array or read from the array in accordance with a particular memory operation. Since the pulse is initiated by detecting a change in one or more of the address bits fed to the SRAM and no other external signal is fed to the SRAM to initiate the control and timing sequence, the circuit is self-timed.
Generally in self-timed circuits once a change has been detected such as an address edge in a SRAM, the pulse generator provides a pulse to initiate the control and timing sequence and enable the memory array to read or write data.
One problem which arises with such circuits is that the timing is very critical. In the event that a valid address is not presented at the output of the address decoder such that the address decoder has provided valid signals on the row and column address lines by the time that the self-timed circuits are activated, data which is to be written to the array will be written at an incorrect location or data which is read from the array will be read from an incorrect location. In either event there will be a faulty memory access.
Generally in self-timed SRAM's, several sources of problems can effect the operation of the SRAM. These differences can arise because of variations in processing conditions between different lots of devices or amongst devices in the same lot. These variations may also arise due to design tolerances being exceeded in actual circuit fabrication.
The first consideration is the decoding of the address lines to the device. If propagation delays through the address decoder are different for different paths and are different between different devices and different lots of such devices, the row and column address lines to the memory array may not be valid at the time that the control and timing circuitry in the device institutes the timing sequence.
A second problem arises when the pulse width of the pulse which initiates the self-timing sequence is too short or to long. If the pulse is too short the memory array may not read or write valid data, whereas if the pulse width is too long the cycle time or period of time at which memory can perform read or write operations is lengthened which is generally undesirable, particularly for high performance systems.
Moreover, the pulse generally has a fixed relationship to the address decoding and enabling of the memory array. Generally the first or leading edge of the pulse is asserted before the address decoding, whereas by the last or trailing edge of the pulse the address must be valid and decoded to provide the proper row and column address signals (since this edge is used to time those control signals used to activate or enable the memory array). This timing sequence can not be interrupted so that it is necessary to ensure that the addresses are valid at the memory array.
A third problem associated with the SRAMs is that the output driver which couples data from the array to a user device such as a bus, is preferably designed to sink or source, depending on the sense of the output driver, relatively high levels of current. For common devices, a large MOS device is used to sink high levels of current. This is desirable because it increases the speed of operation of the memory device. However, if the current sunk is too high a problem occurs since it raises/lowers the levels of the voltages on the power and reference voltage lines. The bouncing of the voltages on these lines can initiate another memory cycle and can lead to oscillations in the memory device. Further, the changes the levels of voltage could cause reduction in noise margin thus corrupting data from the device.